Lecture Series on VLSI Design by Prof S.Srinivasan, Dept of Electrical Engineering, IIT Madras For more details on NPTEl visit nptel.iitm.ac.in
Posts Tagged ‘VLSI’
Lecture 11 – Modeling of Verilog Sequential Circuits
Monday, May 31st, 2010Transaction Level Debug with SystemVerilog VMM & Verdi
Saturday, February 27th, 2010From cvc’s VMM trainings Transaction Level Debug with systemverilog VMM & Verdi
VMM_ass 1
Wednesday, October 28th, 2009assertions system verilog assertions specifying assertions assertions on internal DUT signals assertions on external interfaces assertions coding guidelines reusable assertion based checkers qualification of assertions summery … VLSI Technology engineering
VMM_ass 8
Monday, October 26th, 2009system verilog assertion rules continuation non-synthesizable assertions … VLSI Technology engineering
VMM_ass 2
Sunday, October 25th, 2009property operators in system verilog examples summary of property operators … VLSI Technology engineering
Syestem Verilog 1-18
Friday, October 23rd, 2009Description on Procedural blocks, tasks and functions,always procedural block,system verilog specialized procedural block
system verilog1
Thursday, October 22nd, 2009system verilog assertion . need for assertion . kinds of assertion . system verilog assertion layers property declaration layer assertion directive layer immediate assertion concurrent assertion sequences more on delays
System Verilog 1 – 21
Wednesday, October 21st, 2009Description on operator enhancements Casting,multiple for-loop assignments, bottom setting do while loop,unique case decisions,if else decisions
System Verilog 2 – (sv_guide 9)
Tuesday, October 20th, 2009vectors in sequential logic sensitivity lists .operations in sensitivity list .sequential blocks with begin and end groups .sequential blocks with partial resets .Blocking assignments in sequential procedural blocks .Evaluation of true/false on 4-state values .Mixing up the not operator and invert operator .Nested if-else blocks
System Verilog 1 -3
Monday, October 19th, 2009manipulating data in a sequence . calling subroutines on matches of a sequence .system functions .seven kinds of property .multiple clock support