Describes OVM-SC, the implementation of the Open Verification Methodology within SystemC, which is part of the open-source OVM-ML (Mixed Language) library donated to the OVM community by Cadence
Posts Tagged ‘john’
Using OVM within SystemC
Saturday, May 8th, 2010VMM12 part 1.mpg
Monday, January 11th, 2010An introduction to version 1.2 of the VMM (Verification Methodology Manual) for SystemVerilog, highlighting the new features of VMM 1.2 and the overall conceptual framework. … systemverilog VMM 1.2 verification methodology manual doulos john aynsley
SystemC vs SystemVerilog
Wednesday, September 30th, 2009What is the difference between SystemC and SystemVerilog? This video includes a brief description of these two EDA language standards.