Describes OVM-SC, the implementation of the Open Verification Methodology within SystemC, which is part of the open-source OVM-ML (Mixed Language) library donated to the OVM community by Cadence
Posts Tagged ‘aynsley’
Using OVM within SystemC
Saturday, May 8th, 2010VMM12 part 1.mpg
Monday, January 11th, 2010An introduction to version 1.2 of the VMM (Verification Methodology Manual) for SystemVerilog, highlighting the new features of VMM 1.2 and the overall conceptual framework. … systemverilog VMM 1.2 verification methodology manual doulos john aynsley
SystemC vs SystemVerilog
Wednesday, September 30th, 2009What is the difference between SystemC and SystemVerilog? This video includes a brief description of these two EDA language standards.
SystemVerilog as The New Verilog
Friday, September 25th, 2009Explains how SystemVerilog has become the natural successor to Verilog, and describes some of the features of SystemVerilog borrowed from the C programming language
10 Things about OVM
Thursday, September 10th, 2009Describes ten things you should know about OVM, the Open Verification Methodology for SystemVerilog. This video gives you a top-level technical overview of OVM without diving down into too much language detail. … systemverilog systemc OVM open verification environment doulos aynsley