היום כל אחד חייב להחליט מה הוא יעשה בהייטק. חשוב מאוד לבחור נכון. איך לעשות את זה?? מה יותר טוב? מה יותר מעניין? איפו משכורת יותר גבוה? במה יש יותר עבודה? ומה יש בכלל? מה זה – ASIC Design, FPGA Design, RTL Design, Verification, Verilog and System Verilog, Specman and VCS, Analog VLSI and VLSI LAyout, Back-End and Front-End, RF and RFIC, .NET and Java, Board Design or RT Embedded? … What required in Hightech
הרצאה בנושא קריירה בהייטק: מי נדרש בפיתוח בהייטק?! ..
November 2nd, 2009VMM_ass 1
October 28th, 2009assertions system verilog assertions specifying assertions assertions on internal DUT signals assertions on external interfaces assertions coding guidelines reusable assertion based checkers qualification of assertions summery … VLSI Technology engineering
Contador de 0 a 9 usando palaca de desenvolvimento em FPGA, programada em SystemVerilog
October 27th, 2009VMM_ass 8
October 26th, 2009system verilog assertion rules continuation non-synthesizable assertions … VLSI Technology engineering
VMM_ass 2
October 25th, 2009property operators in system verilog examples summary of property operators … VLSI Technology engineering
DVT – e Language Features
October 24th, 2009This is a demo movie of the e language features in DVT Eclipse. … specman features DVT SystemVerilog System Verilog VHDL Eclipse Java IDE Demo Tutorial
Syestem Verilog 1-18
October 23rd, 2009Description on Procedural blocks, tasks and functions,always procedural block,system verilog specialized procedural block
system verilog1
October 22nd, 2009system verilog assertion . need for assertion . kinds of assertion . system verilog assertion layers property declaration layer assertion directive layer immediate assertion concurrent assertion sequences more on delays
System Verilog 1 – 21
October 21st, 2009Description on operator enhancements Casting,multiple for-loop assignments, bottom setting do while loop,unique case decisions,if else decisions
System Verilog 2 – (sv_guide 9)
October 20th, 2009vectors in sequential logic sensitivity lists .operations in sensitivity list .sequential blocks with begin and end groups .sequential blocks with partial resets .Blocking assignments in sequential procedural blocks .Evaluation of true/false on 4-state values .Mixing up the not operator and invert operator .Nested if-else blocks