February « 2010 « System Verilog Verification

Archive for February, 2010

DVCon 2010 Day3 interview with Matan Vax.mp4

Sunday, February 28th, 2010

Tags: Cadence, dvcon, OOP
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Transaction Level Debug with SystemVerilog VMM & Verdi

Saturday, February 27th, 2010

From cvc’s VMM trainings Transaction Level Debug with systemverilog VMM & Verdi

Tags: asic, CVC, debug, hdl, novas, simulation, systemverilog, verdi, Verification, verilog, vhdl, VLSI, VMM
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