Maven Silicon, Bangalore offers an advanced ASIC verification course for the experienced VLSI engineers and Post Graduates.

Lecture Series on VLSI Design by Prof S.Srinivasan, Dept of Electrical Engineering, IIT Madras For more details on NPTEl visit nptel.iitm.ac.in

Describes OVM-SC, the implementation of the Open Verification Methodology within SystemC, which is part of the open-source OVM-ML (Mixed Language) library donated to the OVM community by Cadence

Start a Verilog project from scratch, enter a simple AND gate design, and compile and download it to a Spartan-3E FPGA board.

In this movie you’ll see a convenient way for controlling OVM field registration. For more info see www.dvteclipse.com

From cvc’s VMM trainings Transaction Level Debug with systemverilog VMM & Verdi

An introduction to version 1.2 of the VMM (Verification Methodology Manual) for SystemVerilog, highlighting the new features of VMM 1.2 and the overall conceptual framework. … systemverilog VMM 1.2 verification methodology manual doulos john aynsley

This is a demo movie of the OVM SystemVerilog Compliance feature in DVT Eclipse.

On-Line Verilog and SystemVerilog training from Computer Based Education. For more information please go to www.computerbasededucation.com … verilog on-line training systemverilog cbe computer based educaton computerbasededucation aldec riviera vcs modelsim incisive nc-sim nc-verilog verilog-xl riviera-pro questa active-hdl active